LIBRARY IEEE;
   USE IEEE.STD_LOGIC_1164.ALL;
   USE IEEE.STD_LOGIC_ARITH.ALL;
   USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  
   ENTITY out_sel IS
   PORT( din_s,din:      in std_logic_vector(17 downto 0);
         dout:           out std_logic_vector(17 downto 0));                 
       END out_sel;       
   ARCHITECTURE BE OF out_sel IS
      
    BEGIN
       dout(15 downto 0)<=din_s(15 downto 0);
       dout(16)<=din(16);
       dout(17)<=din_s(17);       
          
             
   end be;